Anwendung von RFID-Systemen, 2.Auflage German by Christian Kern

By Christian Kern

Die Radio-Frequenz-Identifikation (RFID) erm?glicht den drahtlosen Informationsaustausch zwischen Objekten, Personen, Tieren und dem IT-Netzwerk. Objekte, Personen oder Tiere werden dabei selbst zu Datentr?gern. Leser werden hier in die Lage versetzt, eine RFID-Anwendung von der Idee bis zur Praxis aufzubauen. Wie aktuell das Thema und entsprechend gro? die Nachfrage ist, zeigt das Erscheinen der 2. Auflage nach nur einem Jahr.

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Walker, “Improved wafer-level spatial analysis for IDDQ limit setting,” Proceedings of International Test Conference, 2001, pp. 82–91. [59] A. Keshavarzi, K. Roy, C. F. Hawkins, and V. De, “Multiple-parameter CMOS IC testing with increased sensitivity for IDDQ,” IEEE Transactions on VLSI Systems, vol. 11, pp. 863–870, Oct. 2003. [60] Y. Zorian, “A distributed BIST control scheme for complex VLSI devices,” Proceedings of VLSI Test Symposium, 1993, pp. 4–9. [61] S. Wang and S. K. Gupta, “An automatic test pattern generator for minimizing switching activity during scan testing activity,” IEEE Transactions on Computer-Aided Design, vol.

11] Q. Xu and N. Nicolici, “Modular SoC testing with reduced wrapper count,” IEEE Transactions on Computer-Aided Design, vol. 24, pp. 1894–1908, Dec. 2005. [12] K. Chakrabarty, “Optimal test access architectures for system-on-a-chip,” ACM Transactions on Design Automation of Electronic Systems, vol. 6, pp. 26–49, Jan. 2001. [13] V. Iyengar, K. Chakrabarty, and E. Marinissen, “Test access mechanism optimization, test scheduling and tester data volume reduction for system-on-chip,” IEEE Transactions on Computers, vol.

Lelouvier, “Enhanced reduced pin-count test for full scan design,” Proceedings of International Test Conference, 2001, pp. 738–747. [47] J. Jahangiri, N. Mukherjee, W. T. Cheng, S. Mahadevan, and R. Press, “Achieving high test quality with reduced pin count testing,” in Proceedings of Asian Test Symposium, 2005, pp. 312–317. [48] T. G. Foote, D. E. Hoffman, W. V. Huott, T. J. Koprowski, M. P. Kusko, and B. J. Robbins, “Testing the 500-MHz IBM S/390 Microprocessor,” IEEE Design & Test of Computers, vol.

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