Analog circuit design : high-speed clock and data recovery, by Michiel Steyaert, Arthur H.M. van Roermund, Herman Casier

By Michiel Steyaert, Arthur H.M. van Roermund, Herman Casier

Analog Circuit Design includes the contribution of 18 tutorials of the 17th workshop on Advances in Analog Circuit layout. each one half discusses a selected to-date subject on new and worthwhile layout rules within the sector of analog circuit layout. every one half is gifted by means of six specialists in that box and cutting-edge info is shared and overviewed. This publication is quantity 17 during this winning sequence of Analog Circuit Design.

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C. Pham, J. McDonald, P. 5 Gb/s 32:1/1:32 Sonet Mux/Demux Chip Set”, Proceedings of the ISSCC, IEEE, February 1996, pp. 120–121. 2. R. Walker, C. -S. 488 Gb/s Si-Bipolar Clock and Data Recovery IC with Robust Loss of Signal Detection”, Proceedings of the ISSCC, IEEE, February 1997, pp. 246–247. 3. J. 25-Gb/s Transceiver in 90-nm CMOS”, IEEE JSSC, Vol. 42, No. 12, December 2007, pp. 2745–2757. 4. T. 13 ␮m CMOS”, of the 30th European Solid-State Circuits Conference, September 2004, pp. 487–490. 5.

This increased complexity will require that also an adaptive time step solver algorithm is used to perform the simulation. This will result in a significant increase in system simulation time, making that it is best preserved only for the high-level verification process. Once the architecture has been selected and the building block specifications have been fixed the actual design work at transistor level can start. This will involve the need of a spice like simulator, potentially in combination with an harmonic balance simulator for such properties as phase noise or PSRR.

Three phase rotators, driven by the CDR, generate the three clocks from one I/Q reference. The DFE reconstructs a full-rate data eye from half-rate clocking by means of multiplexers (muxes) in the feedback path (Fig. 12a); to minimize the loop delay, L L BOOST L L L G L L C 10 L L L L L L L A TH Fig. 11 Receiver block diagram DEMUX DFE TH+ CDR 2/4/8/12 Phrot PGA IN Phrot L E 2/4/8/12 10 Phrot L DEMUX L DEMUX I/Q ck L LMS & DR Clock Recovery and Equalization Techniques for Lossy Channels 25 FF CK CK L L ITAP3 MUX MUX FF ITAP2 MUX L L Z G ITAP3 MUX ITAP2 MUX FF IN L MUX L Z G ITAP1 IN FF b) ITAP1 a) L L Fig.

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