Analog-Baseband Architectures And Circuits For Multistandard by Pui-In Mak, Ben U Seng Pan, Rui Paulo Martins

By Pui-In Mak, Ben U Seng Pan, Rui Paulo Martins

With the previous few decade efforts on lithography and integrated-circuit (IC) applied sciences, very inexpensive microsystems were effectively built for plenty of assorted purposes. the craze in instant communications is towards making a networkubiquitous period within the years yet to come. Many unheard of possibilities and demanding situations, akin to layout for multi-standardability and low-voltage (LV) compliance, are quickly changing into the mainstream instructions in wireless-IC learn and improvement, provided that the previous can provide the easiest connectivity between assorted networks, whereas the latter can facilitate the expertise migration into the sub-1-V nanoscale regimes for additional expense and tool aid.

Analog-Baseband Architecturees and Circuits presents architectural and circuit concepts for instant transceivers to accomplish multistandard and low-voltage compliance. the 1st a part of the publication stories the actual layer standards of recent instant conversation criteria, provides the elemental tradeoffs fascinated with transceiver structure choice, and gives case reports of the state of the art multistandard transceivers, the place the foremost thoughts bolstered are highlighted and mentioned. A statistical precis (with a hundred+ references brought up) of so much used transmitter and receiver architectures for contemporary verbal exchange criteria is supplied. all of the references are citied from the top boards, i.e., ISSCC, CICC, VLSI and ESSCIRC, from 1997 to 2005.

The moment half makes a speciality of the architectural layout of multistandard transceivers. A coarse-RF fine-IF (two-step) channelselection strategy is disclosed. It, in the course of the reconfiguration of receiver and transmitter analog basebands, allows not just a rest of the RF frequency synthesizer’s and native oscillator’s layout standards, but additionally a good multistandard compliance by way of synthesizing the low-IF and zero-IF within the receiver; and the direct-up and two-step-up within the transmitter. the primary is confirmed in few layout examples. one in all them is a system-in-a-package (SiP) receiver analog baseband for IEEE 802.11a/b/g WLAN. It not just has the two-step channel choice embedded, but in addition contains a flexible-IF topology, a special 3D-stack floorplan, and a selected layout technique for prime testability and routability.

The 3rd half bargains with the circuit layout. as well as the methodical description of many LV circuit suggestions, three tailormade LV-robust sensible blocks are awarded. They comprise: 1) a double-quadrature-downconversion filter out (DQDF) – it realizes at the same time clock-rate-defined IF reception, I/Q demodulation, IF channel choice and baseband filtering. 2) A switched-current-resistor (SCR) programmable-gain amplifier (PGA) – it deals a transient-free constant-bandwidth achieve adjustment. three) An inside-OpAmp dc-offset canceler – it saves the silicon quarter required for knowing a wide time consistent on chip whereas maximizing its highpass-pole switchability for quick dc-offset transient.

The final half offers experimental result of the three tailored construction blocks and a fully-integrated analog-baseband IC fabricated in a standard-VTH CMOS technique. formerly untold on-/off-chip co-setup for either full-chip and construction blocks measurements are defined. not just the construction blocks have effectively prolonged the cutting-edge boundary when it comes to sign bandwidth and provide voltage, the analog-baseband IC has been thus far the lowest-voltage-reported resolution for IEEE 802.11a/b/g WLAN receivers.

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Again, the image is eliminated through signal cancellation rather than filtering. Since the image is the desired channel itself, the demanded I/Q matching is practically achievable for most applications. , dc offset and 1/f noise. With them superimposed on the desired channel, a substantial degradation in signal-to-noise ratio (SNR) or completely desensitizing the system due to a large baseband gain may result. A capacitive coupling and a servo loop are common choices to alleviate this problem, but at the expense of long settling time and large chip area for realizing the very low cutoff-frequency highpass pole.

94–95, Feb. 2004. 92] M. 11a/b/g WLAN, IEEE International Solid-State Circuits Conference (ISSCC), Digest of Technical Papers, pp. 96–97, Feb. 2004. 93] Z. 11a/b/g WLAN, IEEE International Solid-State Circuits Conference (ISSCC), Digest of Technical Papers, pp. 98–99, Feb. 2005. 94] T. , “A Low-Power Dual-Band Triple-Mode WLAN CMOS Transceiver,” IEEE International Solid-State Circuits Conference (ISSCC), Digest of Technical Papers, pp. 100–101, Feb. 2005. 95] A. 4/5 GHz, 90nm CMOS System in a Package Transceiver for Next Generation WLAN,” IEEE Symposium on VLSI Circuits (VLSI), Digest of Technical Papers, pp.

Der and B. Razavi, “A 2GHz CMOS Image-Reject Receiver with Sign-Sign LMS Calibration,” IEEE International Solid-State Circuits Conference (ISSCC), Digest of Technical Papers, pp. 294–295, Feb. 2001. 31] R. , “A Direct Conversion Receiver for the 3G WCDMA Standard,” in Proc. IEEE Custom Integrated-Circuit Conference (CICC), pp. 239–242, May 2002. 32] J. Rogin, I. Kouchev and Q. 13µm CMOS,” IEEE International Solid-State Circuits Conference (ISSCC), Digest of Technical Papers, pp. 268–269, Feb. 2003.

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